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Freescale Semiconductor /MK70F15WS /PORTB /GPCLR

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Interpret as GPCLR

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https://regviz.com/r/Freescale Semiconductor/MK61F15WS/PORTB/GPCLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GPWD0GPWE

Description

Global Pin Control Low Register

Fields

GPWD

Global Pin Write Data
GPWE

Global Pin Write Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data